This proposed method is targeted to XILINX Virtex-6 FPGA. This proposed approach is based on considering various taps associated with Slow LFSR and Normal LFSR modules. Using the advantages of LFSR in producing pseudorandom pattern, it is considered for SoC testing. This paper considers Linear Feedback Shift Register (LFSR) with various tap to address the above problem. This huge test data volume and its transition time is becoming one of the major problems in association with SoC design testing. Systems-on-Chip (SoC) based design rapidly involves various challenges like huge test data volume, test transition time, area overhead and test data storage.
International Conference on Modeling, Optimization and Computingĭesign and Analysis of Linear Feedback Shift Register based Available online at Procedía Engineering
0 kommentar(er)
